Wafer Level Packaging (WLP) technology uses a wafer reconstruction process, where Known Good Die (KGD) and other types of devices, packages or components are placed side-by-side and embedded with epoxy mold compound. This is followed by a thin-film processing, repassivation and metallization on one or both sides of the wafer to fan out interconnections from original die pads to external pad locations.

The KGD are mounted face down on a carrier with sticky tape.  Molding compound is added then baked to set the compound.  The carrier is then turned right side up and the carrier and sticky tape are removed.

Fan-out wafer level packaging (FOWLP) uses mold compound to embed various functional dies.

Photo Source: Beth Keser

YES polyimide cure ovens offer a vacuum thermal cure that is a critical step for FOWLP and offers:

  • Gentle vacuum process
  • Reduction in particles
  • Shorter process time
  • Less Nitrogen used
  • No discoloration
  • No trapped solvent
  • No outgassing at metallization

FOWLP Advantages

  • Increased I/O density
  • Smaller form factor
  • Multiple die in a low-profile package
  • Excellent electrical and thermal performance
  • Excellent high temperature warpage performance
  • Multi-layer RDL with FOWLP
  • Improved board-level reliability

As dielectric materials have evolved to meet the challenges of WLP, the need for a perfect cure became a critical step.






Needed results for a proper cure:

  • Excellent thermal, electrical and mechanical properties
  • Stability
  • Reliable multi-level interconnections
  • Proper cross-linking
  • No stress
  • No cracking or lifting
  • Controlled glass transition stage
  • Complete evaporation of effluents
  • Highest yields

A proper cure time and temperature ramp rate IMPROVES STABILITY!

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News & Updates

  • Solutions for Nano and Micro-Structured Optical Films (pdf)
  • Medical Device Industry White Paper (pdf)
  • Genomics White Paper (pdf)
  • October 22-23, 2019 - Visit YES at Booth #39 at the International Wafer Level Packaging Conference at the San Jose Doubletree Hotel
  • October 7-9, 2019 - Visit YES at Booth #8 at Lab On a Chip at the Coronado Island Marriott Resort & Spa (San Diego, CA)
  • July 9-11, 2019 - Visit YES at booth #932 at Semicon West in San Francisco
  • June 25-27, 2019 - Visit YES at booth #244 at Sensors Expo and Conference in San Jose
  • May 28-31, 2019 - Visit YES at booth #219 at ECTC in Las Vegas
  • April 29-May 2, 2019 - Visit YES at booth #306 at CS Mantech in Minneapolis
  • March 4-7, 2019 - Visit YES at Booth #64 at the IMAPS Device Packaging Conference in Arizona

Other Updates


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About Our Company

Located in Livermore, California, Yield Engineering Systems (YES) is a privately held company that manufactures engineering process control equipment to meet the needs of innovative engineers and lab managers.